1. Field of the Invention
The present invention relates to memory systems for computers and, more particularly, new cache memory systems for increasing data access speed and efficiency.
2. Art Background
In many data processing systems, it is common to utilize a high speed buffer memory, referred to as a "cache" coupled to a central processing unit (CPU) to improve the average memory access time for the process. The use of a cache is based upon the premise that over time, a data processing system will access certain localized areas of memory with high frequency. The cache typically contains a subset of the complete data set disposed in the main memory, and can be accessed very quickly by the CPU without the necessity of reading the data locations in the main memory.
Many cache systems use multiple levels of cache memories, with data transfer between them. For example, the level 1 cache closest to the CPU may request data from a larger level 2 cache. In order to improve efficiency, the minimum amount of data transferred (referred to as a "line") may contain 64 bits and a line may consist of 256 bits. Although the CPU has developed the ability to handle more bits, most data bus systems coupling the CPU with memory or coupling between memories comprise a series of data lines less than the number of bits in a line. Accordingly, computer systems in which the data transferred constitutes more bits than the width of the data bus must multiplex the data on the bus.
As will be described, the present invention provides methods and apparatus for multiplexing "chunks" of data a full line of data to be read from a cache or other memory.